What’s next in TLineSim development??                                 (Tom Clupper 8/11/08)

  

Here is my “To-Do” list for TLineSim. If you have suggestions, please email me.

 

Current activity:

 

1)      Currently, re-writing the computational engine

a)      Replacing “Classes” with “Structures” where it makes sense

b)      Cleaning up the organizational flow

c)      Change the .sim file format for expandability

i)        May consider XML (open for suggestions)

d)      I hope to have this completed by end of September 2008

2)      Work on SI Note concerning the following S-parameter issues

i)        Frequency domain issues

(1)   Phase vs. group delay

(a)    Number of points

(2)   Scalloping loss

(a)    Return loss

(b)   Structural return loss

(c)    Resonances

(d)   Number of points

ii)       Time domain issues

(1)   Aliasing

(a)    Long bit patterns from arbitrary stimulus

(2)   Bandwidth vs. effective rise time

iii)     Frequency translation using cubic-spline

3)      Update S-parameter element from information above

a)      Translate S-parameters to a different frequency set

i)        Use cubic-spline of  Mag/Angle, or Real/Imag

b)      Check for passivity

i)        Within a specified accuracy (i.e. 10-5, 10-6, or dB level)

c)      Check for reciprocity

d)      Check for lossless

e)      Add ability to import Ver 2 of Touchstone

f)        Change Tab, etc. delimiters to spaces to make compatible with Touchstone

4)      Figure out a fix for the impedance/rho offset in Step mode for very lossy lines

a)      This is a natural artifact of using FFT for Step function stimulus

 

Future activity (pretty much in order):

 

1)      Check on the number of decimal places on frequency axis output

2)      Fix Group Delay format

a)      Totalize phase first before applying a wide aperture

b)      Add group delay estimates

i)        Need to add a least squares fit to totalized phase

3)      Add an arbitrary conductivity option to metal losses

4)      Add Port Extension (Electrical delay) option

a)      Include Phase offset

b)      Maybe on DUT screen

5)      Include Time and Frequency domain “Gating” to VNA output

a)      This will use the Markers in the time domain to set the gate stop and start

6)      Add surface roughness loss correction to Microstrip and Stripline models.

a)      I will also look into adding it for coax and waveguide.

7)      Consider adding an “Arbitrary Waveform Generator” that will take a piece-wise linear source definition (like SPICE would) and create a waveform from it.

a)      Research IBIS models and if they could be used to define the source and load impedance characteristics.

b)      Add ability to create a 2^7-1 bit pattern with different rise and fall time characteristics

c)      This may correct the 1 time-step jitter that is present with the current bit-pattern generator

8)      Develop a “Synthesis” element that will use existing elements

a)      Develop various synthesis elements

i)        Attenuator / pad

(1)   Using ladder network element

ii)       Tank circuit

(1)   Using ladder network element

iii)     Generic connector

(1)   Using Tline element

iv)     Cable specifier

(1)   Using tline element

(2)   Extract model of cable from TDR and S-parameter data

(3)   Get standard cables from database of characteristics

b)      Add an “element block” feature that is similar to the synthesis element, but allows the user to group blocks of elements together in one new “block” element.

i)        This will save space on the DUT screen

 

Potential future activity (not on current radar screen):

 

1)      Add a “Pop-up” summary display page that shows the DUT elements and their parameters.

2)      Export DUT schematic (as best as can be translated) to a SPICE netlist.

a)      Very helpful for Ladder network verification

b)      Won’t be able to do the lossy transmission lines

c)      Convert physical transmission lines to TLine segment

d)      Support ADS, HSpice, LTSPice

3)      I started to investigate PCB vias, but did not find an adequate closed form expression for a model in order to create a “Via” element.

a)      For now, the user will just have to use the ladder and stub element to create a VIA model.

4)      Improvements to Bit-Pattern generator

a)      Add PWLS option to bit pattern creation

i)        This will fix the 1 bit shift

b)      Consider adding more possible bits to bit pattern (currently 128)

i)        This will affect max electrical length for device and min rise time.

ii)       Practically, the max would be 2^9-1 PRBS, or 512 Bits

c)      Add the ability for the user to upload their own bit-pattern.

d)      I started looking into adding “eye masks” to the output, but there were too many variants to make it an easy addition.  If this is important, please email.

5)      Look into providing a Log X frequency scale for the output of the VNA and Spec. Ana.

6)      Consider adding a “Sweep generator” source that would only have a “Spectrum Analyzer” option. It would be like a tracking generator.

7)      Have a “re-define” port option within the DUT.  This would allow the user to set Port 1 and Port 2 anywhere within the DUT.

a)      New terminal would show location of Port

b)      Maybe have a “port” element in the file structure

8)      Improve the S-parameter element further

a)      Research translation of data from a different frequency subset

i)        Look into Chirp-Z for frequency translation

ii)       Extrapolate beyond top frequency using linear prediction function

iii)     Extrapolate lower than start frequency using lossy cable model

b)      Create 2-port Sdd by extracting data from 4-port S-parameter data

9)      Develop more synthesis elements

a)      Transmission line steps

i)        Coax

ii)       Microstrip

iii)     Stripline

iv)     Waveguide

b)      Other transmission line lumped elements

i)        Coax post

ii)       Waveguide fin

iii)     Waveguide iris

c)      DC block/Bias

d)      Transmission line filters

e)      Transmission line impedance matching

f)        Lumped element impedance matching

g)      Lumped element filter

h)      Transmission line filter

i)        Delay line

i)        SPICE lumped-element transmission line

j)        Rise time filter

k)      Loss equalizer

10)  Improve Coax element

a)      DC / low frequency model

b)      Include plating on conductors

c)      Multiple dielectric rings

d)      Slotted conductor model

11)  Consider adding a dielectric material database

a)      Including frequency dependent losses

b)      Add a parameter extraction that would populate the database from measured data

12)  Consider adding an “Error correction” element

13)  Consider adding an “Antenna Path” element

14)  Consider adding a “Mixer” element

15)  Annotations

a)      Auto-determine frequency if none is available

b)      Pos/Neg widths and duty cycle of pulses

16)  Consider adding derivatives / integrals to output graph

a)      Integrating the time domain impulse response gives you an alternative way to get to step mode response

17)  When this is all done … re-write TLineSim to handle 4-port simulations!!!